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SM5841H
NIPPON PRECISION CIRCUITS INC.
Audio Multi-function Digital Filter
OVERVIEW
The SM5841H is an 8-times oversampling (interpolation) digital filter for digital audio reproduction equipment. It accepts 16 or 18-bit input data, and outputs data in 16, 18 or 20-bit format, making a wide range of interfaces possible. It also features digital deemphasis for 3 sampling frequencies, a noise shaper to reduce quantization noise, a DC offset output and other circuits.
ORDERING INFOMATION
Device SM5841HP SM5841HS Package 18pin DIP 22pin SOP
FEATURES
Functions
s s s s
s
s s s
s s s s
2-channel processing 8-times (8fs) oversampling (interpolation) Digital deemphasis (fs = 48/44.1/32 kHz) Serial input data 2s complement, MSB first, 16/18-bit Serial output data 2s complement, MSB first, 16/18/20-bit 1st-order noise shaper (for 16/18-bit output only) 256fs/384fs system clock selectable Output data DC offset (approximately 0.8%) ON/OFF control TTL-compatible input/outputs 5 V (standard) supply 3.2 V operating voltage Molybdenum-gate CMOS
Filter Characteristics
s
s
s
3-stage DC FIR interpolation filter 1st stage (fs 2fs), 69-tap 2nd stage (2fs 4fs), 13-tap 3rd stage (4fs 8fs), 9-tap IIR deemphasis filter for gain and phase characteristics close to those of analog filters Overflow limiter built-in
APPLICATIONS
s s s s s
Digital amplifiers CD players DAT players DBS systems PCM systems
NIPPON PRECISION CIRCUITS--1
SM5841H
PINOUT
18-pin DIP
PACKAGE DIMENSIONS
18-pin DIP (Unit: mm)
WSL1 CKI CKSL CKO VSS WSL2 DSF1 DSF2 RST
1 2 3 4 5 6 7 8 9
18 17 16 15 14 13 12 11 10
DIN BCKI
6.20 0.25 0 15 7.62TYP
LRCI OFST VDD WCKO DOL DOR BCKO
1.27MAX 2.54TYP 22.05 - 0.30 1.20- 0
+ 0.30 + 0.20 + 0.14
0.51MIN
22-pin SOP
22-pin SOP (Unit: mm)
WSL1 CKI CKSL CKO VSS (NC) (NC) WSL2 DSF1 DSF2 RST
1 2 3
22 21 20
DIN BCKI
13.9 0.3
3.00MIN 5.00MAX
4 5 6 7 8 9 10 11
19 18 17 16 15 14 13 12
OFST (NC) (NC)
7.8 0.3
5.4 0.2
1.8 0.1
VDD WCKO DOL DOR BCKO
0.4 0.1
0.5 0.2
NIPPON PRECISION CIRCUITS--2
0.05 0.05
1.27
0 to 10
SM5841HP SM5841HS
0.45 - 0.05
0.25 0. 05
+ 0.1 0.15 - 0.05
LRCI
SM5841H
BLOCK DIAGRAM
LRCI DIN BCKI
CKSL CKI CKO
System Clock
Input data Interface
RST DSF1 DSF2 WSL1 WSL2
Timing Controller Deemphasis Controler Input/output word length selector
Filter and Attenuation Airthmetic block
OFST
Interface Output date
WCKO DOL DOR BCKO
VSS
VDD
PIN DESCRIPTION
SOP DIP Name I/O1 Input/output data select pins 1 1 WSL1 Ip WSL1 HIGH HIGH 8 6 WSL2 Ip LOW LOW 2 3 4 5 6 7 2 3 4 5 - - CKI CKSL CKO VSS NC NC Ip Ip O - - - System clock input System clock select input. 384fs when HIGH, and 256fs when LOW. System clock output. The CKI is first buffered before output on CKO. Ground No connection No connection Deemphasis select inputs 9 7 DSF1 Ip DSF1 LOW LOW 10 8 DSF2 Ip HIGH HIGH 11 12 9 10 RST BCKO Ip O DSF2 LOW HIGH LOW HIGH Deemphasis On On Off On Sampling frequency 44.1 kHz 48.0 kHz - 32.0 kHz WSL2 HIGH LOW HIGH LOW Noise shaper Off On On On Input bit length 18 bits 18 bits 16 bits 16 bits Output bit length 20 bits 18 bits 18 bits 16 bits Description
System reset. Reset and initialization when RST is LOW. Output bit clock
NIPPON PRECISION CIRCUITS--3
SM5841H
SOP 13 14 15 16 17 18 19 20 21 22 DIP 11 12 13 14 - - 15 16 17 18 Name DOR DOL WCKO VDD NC NC OFST LRCI BCKI DIN I/O1 O O O - - - Ip Ip Ip Ip Right-channel 8fs data output Left-channel 8fs data output Output word clock 5 V supply No connection No connection Output data DC offset select input. Summing ON when HIGH, and OFF when LOW. Input data sample rate (fs) clock Input bit clock Input data Description
1. Ip = Input with pull-up resistor
SPECIFICATIONS
Absolute Maximum Ratings
VSS = 0 V
Parameter Supply voltage range Input voltage range Storage temperature range Power dissipation Soldering temperature Soldering time Symbol V DD V IN Tstg PD Tsld tsld Rating -0.3 to 7.0 -0.3 to V DD + 0.3 -40 to 125 250 255 10 Unit V V C mW C s
Recommended Operating Conditions
VSS = 0 V
Parameter Supply voltage range Operating temperature range Symbol V DD Topr Rating 3.2 to 5.5 -20 to 80 Unit V C
NIPPON PRECISION CIRCUITS--4
SM5841H
DC Electrical Characteristics
Standard voltage: VDD = 4.5 to 5.5 V, VSS = 0 V, Ta = -20 to 80 C
Rating Parameter Current consumption HIGH-level input voltage2 LOW-level input voltage2 CKI AC-coupled input voltage HIGH-level input voltage3 LOW-level input voltage3 HIGH-level output voltage4 LOW-level output voltage4 CKI HIGH-level input current CKI LOW-level input current LOW-level input current3 Input leakage current2, 3 Input leakage current2 1. 2. 3. 4. Symbol IDD V IH1 V IL1 V INAC V IH2 V IL2 VOH VOL IIH1 IIL1 IIL2 ILH ILL IOH = -0.4 mA IOL = 1.6 mA V IN = V DD V IN = 0 V V IN = 0 V V IN = V DD V IN = 0 V Sine wave input Condition min V DD = 5.0 V 1 - 0.7VDD - 0.3VDD 2.4 - 2.5 - - - - - - typ - - - - - - - - 10 10 10 - - max 40 - 0.3VDD - - 0.5 - 0.4 20 20 20 1.0 1.0 mA V V V p-p V V V V A A A A A Unit
fSYS = 384fs = 20 MHz, no output load Pins CKSL, OFST Pins LRCI, DIN, BCKI, DSF1, DSF2, WSL1, WSL2, RST Pins CKO, DOL, DOR, BCKO, WCKO
Low voltage: VDD = 3.2 to 4.5 V, VSS = 0 V, Ta = -20 to 80 C
Rating Parameter Current consumption HIGH-level input voltage2 LOW-level input voltage2 CKI AC-coupled input voltage HIGH-level input voltage3 LOW-level input voltage3 HIGH-level output voltage4 LOW-level output voltage4 CKI HIGH-level input current CKI LOW-level input current LOW-level input current3 Input leakage current2, 3 Input leakage current2 1. 2. 3. 4. Symbol IDD V IH1 V IL1 V INAC V IH2 V IL2 VOH VOL IIH1 IIL1 IIL2 ILH ILL IOH = -0.2 mA IOL = 0.8 mA V IN = V DD V IN = 0 V V IN = 0 V V IN = V DD V IN = 0 V Sine wave input Condition min V DD = 3.4 V 1 - 0.7VDD - 0.3VDD 2.4 - 2.5 - - - - - - typ - - - - - - - - - - - - - max 20 - 0.3VDD - - 0.5 - 0.4 12 12 12 1.0 1.0 mA V V V p-p V V V V A A A A A Unit
fSYS = 384fs = 18.5 MHz, no output load Pins CKSL, OFST Pins LRCI, DIN, BCKI, DSF1, DSF2, WSL1, WSL2, RST Pins CKO, DOL, DOR, BCKO, WCKO
NIPPON PRECISION CIRCUITS--5
SM5841H
AC Electrical Characteristics
Clock (CKI) Standard voltage: VDD = 4.5 to 5.5 V, VSS = 0 V, Ta = -20 to 80 C
Condition Parameter Symbol CKSL HIGH HIGH-level clock pulsewidth tCWH LOW HIGH LOW-level clock pulsewidth tCWL LOW HIGH Clock pulse cycle tCI LOW System clock 384fs 256fs 384fs 256fs 384fs 256fs min 23 35 23 35 50 76 Rating Unit typ - - - - - - max 250 ns 500 250 ns 500 500 ns 1000
Low voltage: VDD = 3.2 to 4.5 V, VSS = 0 V, Ta = -20 to 80 C
Condition Parameter Symbol CKSL HIGH HIGH-level clock pulsewidth tCWH LOW HIGH LOW-level clock pulsewidth tCWL LOW HIGH Clock pulse cycle tCI LOW System clock 384fs 256fs 384fs 256fs 384fs 256fs min 25 50 25 50 54 108 Rating Unit typ - - - - - - max 250 ns 500 250 ns 500 500 ns 1000
over 0.7xVDD CKI 0.5xVDD under 0.3xVDD
tCWH tCI
tCWL
NIPPON PRECISION CIRCUITS--6
SM5841H
Serial input timing (BCKI, DI, LRCI)
VDD = 3.2 to 5.5 V, VSS = 0 V, Ta = -20 to 80 C
Rating Parameter BCKI HIGH-level pulsewidth BCKI LOW-level pulsewidth BCKI pulse cycle DIN setup time DIN hold time Last BCKI rising edge to LRCI edge LRCI edge to first BCKI rising edge Symbol min tBCWH tBCWL tBCY tDS tDH tBL tLB 50 50 100 50 50 50 50 typ - - - - - - - max - - - - - - - ns ns ns ns ns ns ns Unit
tBCY tBCWH BCKI tDS DIN tBL LRCI tLB 1.5V tDH 1.5V tBCWL 1.5V
Reset timing (RST) VDD = 3.2 to 5.5 V, VSS = 0 V, Ta = -20 to 80 C
Rating Parameter Symbol Condition min At power-ON RST LOW-level reset pulsewidth tRST At all other times 1 50 typ - - max - - s ns Unit
Control inputs (DSF1, DSF2) VDD = 3.2 to 5.5 V, VSS = 0 V, Ta = -20 to 80 C
Rating Parameter Rise time Fall time Symbol tr tf Condition min 10 to 90% level 90 to 10% level - - typ - - max 100 100 ns ns Unit
NIPPON PRECISION CIRCUITS--7
SM5841H Output timing Standard voltage: VDD = 4.5 to 5.5 V, VSS = 0 V, Ta = -20 to 80 C, CL = 15 pF
Rating Parameter CKI to CKO delay CKI to BCKO delay Symbol tCKO tsbH tsbL BCKO to DOL, DOR, WCKO delay tbdH tbdL RST to DOL, DOR delay trdH trdL Condition min CKI fall to CKO fall CKI fall to BCKO rise CKI fall to BCKO fall BCKO fall to output rise BCKO fall to output fall RST fall to output fall RST rise to output rise - 10 10 0 0 - - typ - - - - - - - max 30 60 ns 60 20 ns 20 40 ns 40 ns Unit
Low voltage: VDD = 3.2 to 4.5 V, VSS = 0 V, Ta = -20 to 80 C, CL = 15 pF
Rating Parameter CKI to CKO delay CKI to BCKO delay Symbol tCKO tsbH tsbL BCKO to DOL, DOR, WCKO delay tbdH tbdL RST to DOL, DOR delay trdH trdL Condition min CKI fall to CKO fall CKI fall to BCKO rise CKI fall to BCKO fall BCKO fall to output rise BCKO fall to output fall RST fall to output fall RST rise to output rise - 10 10 0 0 - - typ - - - - - - - max 45 100 ns 100 30 ns 30 60 ns 60 ns Unit
CKI (CKSL = L)
Tsys
CKI (CKSL = H) 0.5VDD
tsbH
tsbL
1.5V
BCKO
tbdL
1.5V DOL DOR WCKO
tbdH
1.5V
NIPPON PRECISION CIRCUITS--8
SM5841H
Filter Characteristics
8-times interpolation filter
Frequency Parameter f Passband attenuation 0 to 0.4535fs Passband ripple 0.5465fs to 3.4535fs Stopband attenuation 3.4535fs to 4.5465fs 4.5465fs to 7.4535fs 24.1 to 152 kHz 152 to 201 kHz 201 to 328 kHz 0 to 20 kHz @ fs = 44.1 kHz min - -0.03 53 50 53 typ 0.20 - - - - max - +0.03 - - - Rating (dB)
8fs filter response with deemphasis OFF
0
Attenuation (dB)
20 40 60 80 100 120 0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
Frequency (fs)
8fs filter passband response with deemphasis OFF
-0.0001
Attenuation (dB)
-0.00005 0.00000 0.00005 0.0001 0.000 0.125 0.250 0.375 0.500
Frequency (fs)
8fs filter band transition response with deemphasis OFF
0 10
Attenuation (dB)
20 30 40 50 60 70 0.440 0.465 0.490 0.515 0.540 0.565 0.590 0.615 0.640
Frequency (fs)
NIPPON PRECISION CIRCUITS--9
SM5841H Deemphasis filter
Sampling frequency Parameter 32 kHz Passband bandwidth (kHz) Deviation from ideal characteristic1 Attenuation (dB) Phase, () 0 to 14.5 -0.40 to +0.40 -2 to 19 44.1 kHz 0 to 20.0 -0.05 to +0.15 -1 to 15 48 kHz 0 to 21.7 -0.30 to +0.05 -1 to 14
1. The maximum deviation from an ideal filter with 0 dB attenuation and 0 phase characteristics for a 1 kHz input signal.
Passband response with deemphasis ON (fs = 44.1 kHz)
0 Attenuation (dB) 2 4 6 8 10 10 20 50 100 200 500 1k 2k 5k 10k 20k
Frequency (Hz)
Passband response with deemphasis ON (fs = 32/48 kHz)
0 Attenuation (dB) 2 4 6 8 10 10 20 50 100 200 500 1k 2k 5k 10k 20k 48kHz 32kHz
Frequency (Hz)
NIPPON PRECISION CIRCUITS--10
SM5841H
FUNCTIONAL DESCRIPTION
The basic arithmetic block is shown in figure 1, and the function of each block is described in the following sections.
Input fs
Deemphasis IIR filter fs
fs
Attenuator fs 1st FIR 69th - order 2 x interpolator 2fs 2nd FIR 13th - order 2 x interpolator 4fs 3rd FIR 9th - order 2 x interpolator 8fs Output
Figure 1. Arithmetic block diagram
8-times Oversampling (Interpolation)
The interpolation arithmetic block is comprised of 3 cascaded, 2-times FIR interpolation filters, as shown in figure 1. The input signal is sampled at rate fs, and then 8times oversampling data is output. Sampling noise in the 0.5465fs to 7.4535fs stopband is removed by the interpolation filter.
Digital Deemphasis (DSF1, DSF2)
The digital deemphasis filter has the same construction as analog filters. It is implemented as an IIR filter to faithfully reproduce the gain and phase characteristics of standard analog deemphasis filters. The filter coefficients for fs = 32.0/44.1/48.0 kHz sampling frequency are selected by DSF1 and DSF2 when the sampling frequency is specified, as shown in the following table.
DSF1 LOW LOW HIGH HIGH DSF2 LOW HIGH LOW HIGH Deemphasis On On Off On Sampling frequency 44.1 kHz 48.0 kHz - 32.0 kHz
NIPPON PRECISION CIRCUITS--11
SM5841H
System Clock (CKI, CKO, CKSL)
Two system clock frequencies, 384fs and 256fs, can be used. The clock is input on CKI. The CKI input inverter has a feedback resistor to allow AC-coupled input clocks. The system clock is also buffered and then output on CKO. The system clock frequency selection and the internal clock frequency are shown in the following table.
CKSL Parameter HIGH CKI input system clock frequency (fSYS ) CKO clock frequency Internal clock frequency Serial output clock frequency 384fs 384fs 128fs 192fs LOW 256fs 256fs 128fs 256fs
CKSL CKSL = H CKI 1/3 1/2 CKO CKSL = L
to timing controller
Internal system clock (128fs)
to timing controller Figure 2. Clock generator circuit
Noise Shaper and I/O Data Length (WSL1, WSL2)
The SM5841H has functions that can be used to suppress the level of requantization noise due to the inherent arithmetic rounding-off that occurs in digital signal processing.
s s
s
16/18-bit input The input interface accepts 16 and 18-bit input source data. That means that if 16-bit source data is digitally processed, for example in a sound field control or other DSP, the output can be input to the SM5841H without the same need for roundingoff, thereby avoiding the requantization noise that would otherwise occur. 16/18/20-bit output The output interface can support 18 and 20-bit output data, making connection to 18 or 20-bit D/A converters possible. As a result, the requantization noise generated after digital processing can be greatly reduced.
Noise shaper function The 1st-order noise shaper processing occurs on the digital filter output. It reduces the requantization noise for 16 and 18-bit input signals to levels inherent in 18 and 20-bit output modes, respectively. The noise shaper does no processing on 20bit output data.
There are 4 input data and output data length combinations possible, selected by the state of WSL1 and WSL2 as shown in the following table.
WSL1 HIGH HIGH LOW LOW WSL2 HIGH LOW HIGH LOW Noise shaper Off On On On Input bit length 18 bits 18 bits 16 bits 16 bits Output bit length 20 bits 18 bits 18 bits 16 bits
NIPPON PRECISION CIRCUITS--12
SM5841H
Audio Data Input (DIN, BCKI, LRCI)
The input data is in 16/18-bit serial, 2s complement, MSB first format. Serial input data on DIN is clocked into an SIPO (serial in, parallel out) register on the rising edge of the BCKI bit clock, and then converted to parallel data. SIPO output data is transferred into the left and right-channel input registers on the falling edge and rising edge, respectively, of the LRCI clock. The internal arithmetic operation and output circuit timing is independent of the input timing. Accordingly, phase differences between LRCI, BCKI and CKI do not affect device operation, and any jitter in the data input clock does not cause jitter in the output clock. Note that the device should be reset if either or both of the LRCI and CKI clocks stop. If the device is not reset, even though the clocks are low frequency, incorrect circuit operation may occur, generating unwanted output noise.
1/fs
Lch
MSB 16 / 18bit LSB
Rch
MSB
16 / 18bit
LSB
DIN BCKI LRCI
Figure 3. Audio data input timing
NIPPON PRECISION CIRCUITS--13
SM5841H
Audio Data Output (DOL, DOR, BCKO, WCKO, OFST)
The output data is in 16/18/20-bit serial, 8fs, simultaneous left and right-channel, 2s complement, MSB first format. A DC offset can be added to arithmetic data before the data is output to reduce the D/A converter zerocrossing distortion for very small input signals. The offset added is approximately 0.8% of full-scale for the corresponding output bit length, as shown below.
s s s
512 LSB for 16-bit output 2048 LSB for 18-bit output 8192 LSB for 20-bit output
8fs serial data is output on independent DOL and DOR channels, in sync with the falling edge of the internal system clock and BCKO clock. The number of BCKO bit clock pulses per word changes depending on the output bit length selected (16/18/20 bits). Consequently, output data is latched into the D/A converter internal register on the falling of the edge of an output word clock WCKO, which has timing independent of the number of output bits as specified in the following table.
Parameter Bit clock rate Data word length Symbol TB TDW CKSL = HIGH tSYS (1/192fs) 24TB CKSL = LOW tSYS (1/256fs) 32TB
The DC offset is added to the output when OFST is HIGH. DC offset is OFF when OFST is LOW.
System Clock BCKO DOL or DOR WCKO
6TB TDW = 24TB The number of output bits is determined by the output bit length selected. 18TB
TB
12345
11 12 13 14 15 16 17 18 19 20
1234
Figure 4. 8fs data output timing (CKSL = HIGH)
System Clock BCKO DOL or DOR WCKO
6TB TDW = 32TB
The number of output bits is determined by the output bit length selected.
TB
12345
11 12 13 14 15 16 17 18 19 20
1234
26TB
Figure 5. 8fs data output timing (CKSL = LOW)
NIPPON PRECISION CIRCUITS--14
SM5841H
System Reset and Output Muting (RST)
System reset The SM5841H must be reset at power-ON by applying a LOW-level pulse on RST. At system reset, the arithmetic and output timing counters are reset on the next LRCI start edge, as long as the CKI clock has already stabilized. The power-ON reset pulse can be applied by a microcontroller or, for systems where CKI and LRCI are stable at power-ON, by connecting a 300 pF capacitor between RST and VSS. For systems that do not use a microcontroller, the capacitor must be chosen such that the CKI and LRCI clocks fully stabilize before RST goes from LOW to HIGH. If the system clock is interrupted or is corrupted by jitter, after power-ON reset and all internal timing is synchronized, such that a timing error greater than 3/8 x fLRCI occurs, the internal timing is automatically reset on the next LRCI start edge. This resynchronization affects the internal operation and can generate a momentary click noise output. Output muting When RST goes LOW, the DOL and DOR outputs go LOW, immediately muting the output signal, and they remain LOW for intervals in word units. Muting is released and timing is synchronized on the 3rd rising edge of LRCI after RST goes HIGH. Note that during muted output, the BCKO and WCKO clocks do not stop.
RST LRCI Internal reset DOL DOR
(L) 1 2 3 4
(L)
Figure 6. System reset timing and output muting
NIPPON PRECISION CIRCUITS--15
SM5841H
TIMING DIAGRAMS
Input Timing Examples (DIN, BCKI, LRCI)
Audio ICs
(MSB)
18bit Lch
(LSB)
(MSB)
18bit Rch
(LSB)
DIN BCKI LRCI
1 / fs
Figure 7. 18-bit input timing
(MSB)
16bit Lch
(LSB)
(MSB)
16bit Rch
(LSB)
DIN BCKI LRCI
1 / fs
Figure 8. 16-bit input timing
NIPPON PRECISION CIRCUITS--16
SM5841H
Output Timing Examples (DOL, DOR, BCKO, WCKO)
System Clock BCKO DOL or DOR WCKO
6TB TDW = 24TB 18TB
TB
12345
11 12 13 14 15 16 17 18 19 20
1234
The number of output bits is determined by the output bit length selected.
Figure 9. 8fs data output timing (CKSL = HIGH)
System Clock BCKO DOL or DOR WCKO
6TB TDW = 32TB
The number of output bits is determined by the output bit length selected.
TB
12345
11 12 13 14 15 16 17 18 19 20
1234
26TB
Figure 10. 8fs data output timing (CKSL = LOW)
NIPPON PRECISION CIRCUITS--17
SM5841H
APPLICATION CIRCUITS
Input Interface Circuits
C16M SONY CXD2500 LRDK DA16 DA15
16.9344MHz 44.1kHz 2.1168MHz
CKI LRCI DIN BCKI
CKSL SM5841H
PSSL
WSL1
XCK MATSUSHITA MN6617
16.9344MHz
CKI LRCI DIN
CKSL SM5841H
R / L 44.1kHz 2.1168MHz
SRDATA SEL IPSEL SRCK
BCKI
WSL1
OA YAMAHA YM3623 L/R DO BCO
16.9344MHz 44.1kHz 2.1168MHz
CKI LRCI DIN BCKI
CKSL SM5841H
WSL1
17MO TOSHIBA TC9200F CHCK DOUT BCK
16.9344MHz 44.1kHz 2.1168MHz
CKI LRCI DIN BCKI
CKSL SM5841H
WSL1
NIPPON PRECISION CIRCUITS--18
SM5841H
Output Interface Circuits
18-bit, 2-DAC (8fs L+R output mode)
WCKO DOL SM5841H (16bit Input) DOR BCKO WSL1
CLOCK BURR - BROWN L. E. PCM58P DATA CLOCK BURR - BROWN L. E. PCM58P DATA
Lch OutPut
Rch OutPut
This example is for 16-bit input mode, so WSL1 is tied HIGH. For 18-bit mode, WSL1 is tied LOW.
16-bit, 1-DAC (8fs L+R output mode)
SM5841H (16bit Input)
WCKO DOL DOR BCKO
WCKO LSI NEC PD6376 RSI CLK 4/8fs SEL
Lch Output Rch Output
WSL1
WSL2
NIPPON PRECISION CIRCUITS--19
SM5841H
NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter, including compliance with export controls on the distribution or dissemination of the products. Customers shall not export, directly or indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. 4-3, Fukuzumi 2-chome Koto-ku, Tokyo 135-8430, Japan Telephone: 03-3642-6661 Facsimile: 03-3642-6698
NIPPON PRECISION CIRCUITS INC.
NC9625AE
1998.06
NIPPON PRECISION CIRCUITS--20

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